Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)

Fault Tolerance Techniques For Sram Based Fpgas (Frontiers In Electronic Testing) 2006
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De Micheli. Jeffery and R. Towards byzantine fault tolerance in many-core computing platforms. In Dependable Computing, PRDC Springer-Verlag New York, Inc. Laredo, P. Bouvry, D. Arenas, J. Merelo, and C. Designing robust volunteer-based evolutionary algorithms. Genetic Programming and Evolvable Machines, 15 3 —, Lee, Jing Tao, and Yang Zhao. Scientific Workflow Management and the Kepler System. Concurrency and Computation: Practice and Experience, 18 10 —, Mange, M. Sipper, A. Stauffer, and G. Toward robust integrated circuits: The embryonics approach. Ontologies for describing the context of scientific experiment processes.

Design of a fault-tolerant dram with new on-chip ecc. Springer US, Framework for verification of preserved and redeployed processes. Taverna, reloaded. Gertz, T. Hey, and B. On-the-fly calibrating strategies for evolutionary algorithms.

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Vijaykrishnan, and C. Exploring fault-tolerant network-on-chip architectures. In Dependable Systems and Networks, DSN Don't have an account?

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Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications

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Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) [Fernanda Lima Kastensmidt, Ricardo Reis] on snakwalldeha.ga *FREE*. Frontiers in Electronic Testing Fault-Tolerance Techniques for SRAM-Based FPGAs In the sequence, it shows the main fault tolerance techniques used.

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